1. Field of the Invention
The invention relates to a testing system and a testing method for DUTs (devices under test), and more particularly, to a testing system and a testing method having fewer testing pads for DUTs.
2. Description of the Prior Art
It is well-known that, in the manufacturing process of ICs (integrated circuits) and chips, a testing operation is a commonly used step. Each IC, whether the IC is in the wafer state or in the packaging state, has to be tested through a standard testing procedure to ensure functions of each circuit of the IC. Generally speaking, accuracy and speed of a testing procedure are required because of two main concerns: new design of ICs and yield. For example, as IC design progresses, the ICs may have more functions, meaning that the inner circuits of the ICs become more complicated. Therefore, the accuracy of the testing procedure also becomes more essential.
The testing procedure of testing a single die of a wafer in the above-mentioned wafer state is also called wafer probing. As known by those skilled in the art, wafer probing is an essential test in manufacturing, and it is mainly used to detect device characteristics of each die on the wafer by establishing a temporary electronic contact between an external testing device and the dies on the wafer. Therefore, good ICs (that is, the produced ICs that conform to the needed specification) are selected from the whole wafer before all dies are separated and packaged. Furthermore, the yield of the wafer can be determined through the wafer probing. Therefore, engineers could know the problems of wafer manufacturing by analyzing the yield. In other words, if the yield is a high percentage, this means that the manufacturing procedure is correct, otherwise, if the yield is a low percentage, this means that some problems may have occurred in the manufacturing procedure and some steps of the manufacturing procedure need to be examined again.
Please refer to FIG. 1, which is a diagram of a testing circuit 100 according to the prior art. As shown in FIG. 1, the testing circuit 100 comprises a plurality of DUTs (devices under test) 110, 120, 130, 140 and a plurality of testing pads 150, 160, 170, 180, 190, wherein the DUTs 110, 120, 130, 140 and the testing pads 150, 160, 170, 180, 190 are electrically connected in series. That is, every two DUTS of DUTs 110, 120, 130, 140 share one testing pad of testing pads 150, 160, 170, 180, 190. As known by those skilled in the art, the testing circuit 100 is positioned on a wafer. That is, the testing pads 150, 160, 170, 180, 190 and related conducting lines are formed in the same wafer through a semiconductor manufacturing procedure. In general, the above-mentioned testing pads 150, 160, 170, 180, 190 are metal welded pads or touched by probe pins for establishing the electronic contact between the external testing device (not shown in FIG. 1) and the DUTs 110, 120, 130, 140. Therefore, in the testing operation, the external testing device can establish a testing voltage (or a testing current) on each DUT 110, 120, 130, 140 through the testing pads 150, 160, 170, 180, 190, and detect the corresponding current (or corresponding voltage) in order to detect the device characteristics (for example, the impedance) of the DUTs 110, 120, 130, 140.
However, there is a serious disadvantage in the testing circuit 100 shown in FIG. 1. Because the DUTs 110, 120, 130, 140 and testing pads 150, 160, 170, 180, 190 are connected in series, as shown in FIG. 1, 4 DUTs need 5 testing pads. Following the above illustration, K DUTs need K+1 testing pads on the wafer. Therefore, the testing circuit according to the prior art occupies a huge wafer area because of the huge number of testing pads. In addition, the testing circuit in the prior art also limits the number of DUTs due to the consumption of the wafer area.